ECE-552: Microprocessor Architecture
The final project for
ECE-552 was to implement a processor via schematic design.
Groups were formed from three individuals and were instructed to
implement a given instruction set using a cache. Each gate we
used had a preset cost and delay. Below is a table
representing the final results of all groups; our group is in
highlighted in red. Due to clever logic tricks, resource
management, and cost analysis, our group was able not only to obtain
the fastest speed but also the lowest cost.